Blar i NTNU Open på forfatter "Josephsen, Simon"

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    • An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology 

      Josephsen, Simon (Master thesis, 2013)
      This master?s thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ...

    • An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology 

      Josephsen, Simon (Master thesis, 2013)
      This master thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ...